1. Field of the Invention
The present invention is related to a data-mapping method and cache system for use in a motion compensation system, and more particularly, to a data-mapping method and reconfigurable circular cache system operative based on the frame width for use in a motion compensation system.
2. Description of the Prior Art
The ability to quickly and efficiently process video streams has grown in importance, particularly for portable consumer electronic products incorporating more and more multimedia features but still having somewhat limited function relative to more powerful platforms such as personal computers. The data is often encoded (compressed) to facilitate storage and streaming, and then decoded (decompressed) for playback (e.g., display).
H.264/AVC is a compression standard developed by the Joint Video Team (JVT) of ISO/IEC MPEG (Moving Picture Experts Group) and ITU-T VCEG (Video Coding Experts Group), and provides core technologies for efficient storage, transmission and manipulation of video data in multimedia environments. The focus of H.264/AVC is to develop a standard that achieves, among other results, highly scalable and flexible algorithms and bit-stream configurations for video coding, high error resilience and recovery over wireless channels, and highly network-independent accessibility.
In a typical video sequence, the content of one frame, or a least a portion of that frame, may be very similar to that of another frame. A compression technique commonly referred to as “motion compensation” is employed using a cache memory system to exploit temporal or spatial locality, thereby reducing excess memory access when performing motion compensation. If content in a current frame is closely related to that of another (reference) frame, it is possible to accurately represent, or predict, the content of the current frame using the reference frame instead of accessing the entire current frame. Although operations which require off-chip memory access in an H.264/AVC decoder also include reference picture storing, de-blocking, and display feeding, motion compensation accounts for the largest memory bandwidth and is thus the main consideration for performance improvement.
FIG. 1 is a diagram illustrating a prior art cache memory system 100 for use in a motion compensation system. A frame stored in an external memory 12 is partitioned into blocks of pixels (e.g., macroblocks). Several pixels, stored and accessed together in the external memory 12, are defined as an access unit which may include one macroblock or a plurality of macroblocks. Access units of the external memory 12 are sequentially fetched in a left-to-right and up-to-down direction as indicated by the arrow of FIG. 1. A cache 14 comprising 8 concatenated memory banks MK1-MK8, each of which provides memory storage size equal to one macroblock, is configured to store data loaded from the external memory 12.
An access unit is read from the external memory 12 even when part of it is required, and there exists a high probability that the unwanted part of this access unit will be required soon by subsequent access units. FIG. 2a-2c are diagrams illustrating a prior art data-mapping method for use in the cache memory system 100. In FIG. 2a, an access unit AU1 (represented by the dotted line) includes the wanted macroblock B and the currently unwanted data (represented by the striped area) of the frame F1. Both the current macroblock B and the unwanted part of the access unit AU1 is loaded into the memory banks BK1-BK4 of the cache 14. In FIG. 2b, an access unit AU2 (represented by the dotted line) includes the wanted macroblock C and the currently unwanted data (represented by the shaded and the striped area) of the subsequent frame F2. Both the current macroblock C and the unwanted part of the access unit AU2 represented by the striped area is loaded into the memory bank BK5-BK8 of the cache 14. However, the unwanted part of the access unit AU2 represented by the shaded area has been fetched when loading the previous access unit AU1 and can thus be re-used for decoding the current access unit AU2. Similar operations continue for fetching the same row of frame data into corresponding memory banks. Since which memory bank stores an access unit is determined by the frame width, data conflict may occur in the prior art cache memory system 100. As illustrated in FIG. 2c, an access unit AUn (represented by the dotted line) includes the wanted macroblock F and the currently unwanted data (represented by the shaded and striped area) of the frame Fn. If the access unit AUn is to be loaded into the memory banks BK1-BK4 of the cache 14, the previously loaded reference data (represented by the shaded area) is over-written and thus no longer available for decoding the current access unit AUn. This kind of data conflict severely downgrades cache performance.